Radio Frequency (RF) transmission and reception is central to many modern consumer electronics devices, industrial control systems, communications systems, navigation systems, and the like. One of the key building blocks found in most radio transceivers is a (variable) frequency synthesizer, often implemented as a Phase Locked Loop (PLL). The frequency synthesizer produces an RF output signal with a stable frequency, as compared to a reference frequency source, such as a crystal oscillator. One important application for a frequency synthesizer is use as the local oscillator (LO) in a receiver or transmitter to implement frequency conversion, e.g. of a received signal from RF to baseband, or vice versa for a signal to be transmitted.
Conventionally, PLLs have been implemented in analog domain, with a prescaler, an analog phase detector, a charge pump and an analog loop filter to adjust a Voltage Controlled Oscillator (VCO) to a desired output frequency.
FIG. 1 shows a basic topology of Digital Phase-Locked Loop (DPLL) 10. The DPLL 10 includes a Digital Phase Detection and Filtering block 12, a Digitally Controlled Oscillator (DCO) 14, a Time to Digital Conversion (TDC) block 16, and a reference frequency source 18. The TDC 16 is a quantized phase detector, which detects a phase difference between the output of the DCO 14 and the reference frequency source 18. The quantized phase is compared to a digital reference, i.e., frequency control word (FCW), to form a phase error signal. The phase error is then filtered by a digital loop filter, and used to adjust the DCO 14. Since the reference oscillator 18 defines the sampling rate and time instant at which the DCO 14 output signal is measured, the DCO 14 output frequency will be equal to the reference frequency multiplied by FCW.
The TDC 16 used to quantize the phase difference between the reference clock edge and the DCO edge, must have a fine grain resolution. The DPLL 10 in-band phase noise level is directly proportional to the TDC 16 quantization step. Common implementations of a TDC 16 circuit are based on delay lines, with numerous taps. The resolution is limited to the minimum gate delay available in the implementation technology (e.g., approximately 25 ps in deep sub-micron CMOS). Using delay difference, instead of unit delay, the resolution can be enhanced (known as the Vernier principle). Still, resolution is limited due to analog impairments (e.g. delay mismatch) prohibiting reliable delay difference below 5 ps. State of the art is limited to the range of 5 ps, prohibiting DPLL in-band phase noise floor less than −100 dBc at GHz frequencies.
In addition to achieving limited phase quantization resolution, the delay line based TDCs 16 include numerous circuit components, and are fully analog in design. As well known in the art, analog circuits are challenging to implement in new projects. They also often exhibit a current consumption profile that is difficult to manage, with high peak values.
Prior art TDC 16 solutions rely on using delay line based phase quantization. If the delay is fixed, the quantization noise will rise as function of the DCO 14 output frequency. The number of bits obtained from the TDC 16 can be directly evaluated by
            log      2        ⁡          (              1                              T            d                    ·                      F            DCO                              )        ,where Td represents the delay, i.e. the time measurement resolution, and FDCO represents the frequency of the DCO 14.
Delay may be adjusted relative to FDCO, but in practice this entails an increase in power dissipation as the frequency rises. Increased power dissipation exacerbates clock interference caused by the TDC 16, which may disturb the operation of the DPLL 10. Delay cells create high peak supply currents, and thus it is difficult to maintain the supply voltage of the TDC 16 constant. If the supply voltage varies, it will further modulate the TDC 16 measurement result, and cause unwanted modulation of the DCO 14. The modulation is also channel dependent, which makes it difficult to accurately characterize the phase quantization device. Thus, it is also difficult to implement automated digital algorithms and software calibrations to optimize and remove unwanted components from the output signal.
One example of DPLL implementation using delay line for phase quantization is described in a paper by R. B. Staszewski et al., titled, “All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS,” published in the IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, pp. 2278-2279, December 2004, the disclosure of which is incorporated herein by reference in its entirety.
The Background section of this document is provided to place embodiments of the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.